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Edge142 Per Pin timing Deskew w 4x2 Cross Point Switch
EDGE HIGH-PERFORMANCE PRODUCTS Description
The Edge142 is a 4 X 2 cross point switch with output edge deskew capability. Manufactured in a high performance bipolar process, it is designed primarily for channel deskew applications in VLSI and Mixed-Signal test equipment. Any of the four input signals may be selected as the source for either output. The 142 performs test head multiplexing, adjacent channel multiplexing, and signal buffering for both the drive and receive signals, in addition to timing deskew. The delay value (and resolution) is controlled via an external voltage DAC. The delay element is designed specifically to be monotonic and very stable while delaying a very narrow pulse over a limited delay range. The part offers separate delays for rising vs. falling edges. The rising edge delay range is 1.5 ns and the falling edge adjustment range is 300 ps. The Edge142 is also well suited for 1:2 or 1:4 signal fanout applications that require: - multiple signal sources - output enable / disable - timing deskew on the output signals.
Features
* Very Narrow (<1 ns) Pulse Width Capability * Fmax > 850 MHz * Independent Delay Adjustments for Positive and Negative Transitions * Delay Range of 1.5 ns * Trailing Edge Adjust Range of 300 ps * Small Footprint: 52-pin MQFP Package (10 X 10 mm) with Internal Heat Spreader or Die Form
Applications
* Automatic Test Equipment - Per pin deskew in VLSI, Mixed-Signal, and Memory Testers - Clock Distribution with timing adjustment
Functional Block Diagram
VDELAY 0 VFALL 0
IN0 / 0*
T
OUT0 / 0*
IN1 / 1* 4X2 IN2 / 2* T
2X2
MUX OUT0 / 0* MUX OUT1 / 1*
IN3 / 3*
OUT1 / 1*
VFALL 1 VDELAY 1
Revision 1, February 14, 2000
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description
Pin Name Digital IN0, IN1, IN2, IN3, IN0* IN1* IN2* IN3* 41, 44, 48, 51, 42 45 47 50 The multiplexer input signals. (Differential digital inputs.) Pin # Description
OUT0, OUT* OUT1, OUT1* MUX OUT0, 0* MUX OUT1, 1* S00, S01 S10, S11 MUX0 SEL MUX1 SEL EN* MUX EN Analog VDELAY0 VDELAY1 VFALL0 VFALL1 VMID0 VMID1 REXT1
26, 25 14, 15 23, 22 17, 18 32, 31 8, 9 30 10 29 11
The selected and delayed output signals. (Differential ECL compatible outputs.) Selected monitor outputs. (Differential ECL compatible levels.) Single-ended 10KH ECL compatible inputs which select the channel 0 and channel 1 source. Single-ended 10KH ECL compatible inputs which select the two output monitor sources. Single-ended 10KH ECL compatible input which enables the delayed outputs. Single-ended 10KH ECL compatible input which enables the monitor outputs.
39 1 37 3 38 2 36
Analog voltage inputs which control the amount of propagation delay for each channel. Analog voltage inputs which control the amount of falling edge delay for each channel. Analog voltage inputs which control the amount of pulse width compensation for each channel. Analog input current used to establish the bias current for the VDELAY, VFALL, and VMIDinputs. Analog input current used to establish the bias level for the delay cells. Op Amp compensation capacitors.
REXT2 COMP1, COMP2 TDP, TDN Power GND
4 35 5 21, 19
Positive and negative terminals to the thermal diode string.
6, 12, 13, 16, 24, 27, 28, 34, 40, 43, 49, 52 7, 20, 33, 46
Device ground (positive device supply).
VEE
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description (continued)
MUX0 SEL
VDELAY0
VFALL0
COMP1
REXT1
VMID0
GND
GND 28
39
38
37
26
35
34
33
32
31
30
29
GND IN0 IN0* GND IN1 IN1* VEE IN2* IN2 GND IN3* IN3 GND
40 41 42 43 44 45 46 47 48 49 50 51 52
10 12 13 11 1 2 3 4 5 6 7 8 9
27
GND
VEE
S00
S01
EN*
26 25 24 23 22 21 20 19 18 17 16 15 14
OUT0 OUT0* GND MUX OUT0 MUX PUT0* TDP VEE TDN MUX OUT1* MUX OUT1 GND OUT1* OUT1
MUX1 SEL
VDELAY1
VFALL1
MUX EN
VMID1
REXT2
COMP2
VEE
GND
S11
GND
52-Pin MQFP 10mm x 10mm with Internal Heat Spreader
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GND
S10
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description
Chip Overview The Edge142 is a 4 X 2 cross point switch and deskew element, offering an 1.5 ns delay (Tspan), where the VDELAY inputs adjust the overall propagation delay of the part. In addition, the part supports a separate falling edge delay of 300 ps (Tfall), where the VFALL inputs control the falling edge delay. Two additional outputs, which are selectable from either OUT0 or OUT1, are provided. These outputs are useful when attempting to fanout a selected input to multiple destination without using and external buffer. All output signals may be enabled or disabled. The Edge142 is designed to be monotonic and very stable. Figure 1 shows a simplified block diagram.
S01 S00
VFALL0 VMID0
VDELAY0 MUX0 SEL EN* MUX EN
IN0 / 0*
0
IN1 / 1*
1 T T 0 MUX OUT0 / 0* OUT0 / 0*
IN2 / 2*
2
IN3 / 3*
3
1
1 3 0 2 T 1 T OUT1 / 1* MUX OUT1 / 1*
0 MUX1 SEL S11 S10 VFALL1 VMID1 VDELAY1
Figure 1. Edge142 Block Diagram
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Input Multiplexer The Edge142 offers a 4 X 2 cross point switch in which one of four input signals are selected to two independent outputs. Each output signal's propagation delay and pulse width may then be adjusted via external control. The truth table below documents the multiplexer functionality. Notice that there are no restrictions between the selection of channel 0 and channel 1.
SEL01 0 0 1 1 SEL00 0 1 0 1 OUT0 IN0 IN1 IN2 IN3 SEL11 0 0 1 1 SEL10 0 1 0 1 OUT1 IN0 IN1 IN2 IN3
Output Enable Both the output and multiplexer output signals may be enabled or disabled, as documented below.
EN* 0 1 OUT/OUT* Active 0 MUX EN 0 1 MUX(0,1)OUT 0 Active
Propagation Delay Adjust The Edge142 supports two independent delay functions, which are described in the table below.
Tpd+ VDELAY VFALL 1.5 ns 0 ps Tpd1.5 ns 300 ps
Output Multiplexer The Edge142 provides MUX OUT0 / MUX OUT0* and MUX OUT1 / MUX OUT1*, additional buffered differential output signals. These signals are selected from OUT0 or OUT1, depending on the state of MUX SEL, as indicated in the table below.
MUX(0,1) SEL 0 1 MUXOUT0 OUT0 / OUT0* OUT1 / OUT1* MUXOUT1 OUT1 / OUT1* OUT0 / OUT0*
VDELAY controls the propagation delay of both the rising and falling edge (see Figure 2). An input signal is selected and then delayed by some programmable amount (Tspan) determined by the analog input VDELAY. The rising and falling edges are delayed equally. The propagation delay for a rising and a falling edge is defined as Tpd+, Tpd- = Tpd(nom) + Tspan where Tpd(nom) is the propagation delay of the part with zero programmed delay, and Tspan is the additional delay programmed via the VDELAY input. Notice that Tspan can be either positive or negative, depending on the nominal biasing of VDELAY, thus allowing bidirectional propagation delay adjustment. The transfer function for Tspan vs. VDELAY is shown in Figure 4.
TPD min
The MUX OUT signals allow either of the delayed outputs to be sent to an alternative destination without having to daisy chain the outputs to multiple destinations. This feature permits point to point routing of all critical timing signals in an effort to maintain the cleanest transmission lines for these signals. The MUX OUT signals also provide a method for sending one common selected input signal to two independent destinations. This feature is useful when fanning out driver data and driver enable signals to multiple test heads.
INPUT
TPD min
OUTPUT (VDELAY = +0.1V) Tspan OUTPUT (VDELAY = -1.3V) Tspan
Figure 2. VDELAY Control
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Falling Edge Adjust VFALL allows independent adjustment of the falling edge (see Figure 3). The propagation delay for a falling edge is defined as Tpd- = Tpd(nom) + Tspan + Tfall where Tfall is defined as the additional delay incurred by adjusting the VFALL input. Notice that Tfall can be either positive or negative over a 150 ps range, depending on where VMID is set. This flexibility allows the part to either expand or contract an input signal . Notice also that Tpd+ is a function of VDELAY only, while Tpd- is a function of VDELAY and VFALL. The transfer function for Tspan vs. VDELAY is shown in Figure 4. The transfer function for Tfall vs. VFALL is shown in Figure 5. Default Conditions All digital inputs have either an internal pull up (to ground) or pull down (to VEE) resistor (~50 K) to protect against floating inputs migrating to an indeterminant state. All differential timing inputs are pulled to a logical zero state. All operating mode control inputs are pulled down to a logical zero. The mux select and mux enable inputs have pull down resistors to VEE. And the output enable is pulled up to ground. The following chart summarizes the internal state of the digital inputs.
Input IN0, IN1, IN2, IN3 IN0*, IN1*, IN2*, IN3*
Internal Resistor Pull Down to VEE Pull up to GND Pull Down to VEE Pull Down to VEE Pull Down to VEE Pull up to GND
VMID VMID is used in conjuction with VFALL to remove any systematic pulse width expansion or contraction. VMID and VFALL are differential analog voltage inputs which affect the falling edge delay. When VFALL equals VMID, there will be no programmed pulse width variation between the input and the output signal. It is the difference between VMID and VFALL that expands or contracts a pulse. VMID should be statically established at the midpoint of the voltage swing of VFALL.
INPUT
S00, S10, S01, S11 MUX0 SEL, MUX1 SEL MUX EN EN*
However, despite the internal resistors providing a known default condition, it is recommended that no unused inputs be left floating.
Programming Sequence VDELAY, in addition to affecting the placement of the rising edge, also affects the falling edge. Therefore, when calibrating a system, VDELAY should be adjusted first. As VFALL affects only the falling edge, it should be adjusted after VDELAY is established.
VFALL = +0.1V
VFALL = -1.3V
OUTPUT (-1.3V < VDELAY < +0.1V) TPDmin + Tspan TPDmin + Tspan + Tfall
Figure 3. Falling Edge Control
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Edge142 Tpd+ Span vs. VDELAY; VFALL and VMID=-0.6V
1.6 1.4 1.2
Tspan [ns]
1 0.8 0.6 0.4 0.2 0 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 VDELAY [V] -1 -1.1 -1.2 -1.3
Figure 4. VDELAY Tranfer Function
Edge142 Tpd- Span vs. VFALL; VDELAY and VMID=-0.5V
200 150 100
Tpd- [ps]
50 0 -50 -100 -150 -200 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 VDELAY [V] -1 -1.1 -1.2 -1.3
Figure 5. VFALL Transfer Function
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Analog Delay Inputs VDELAY, VFALL, and VMID are analog voltage inputs which control the delay of the rising and falling edge. All three inputs may vary from +0.1V (minimum delay) to -1.3V (maximum delay). VMID should be permanently set to the middle of the overall voltage range spanned by VFALL (~ -0.6V). A fixed resistor to ground will usually suffice. The exact setting of VFALL will vary depending on the required delay range of the falling edge. These inputs are designed to sink a constant input current, typically 1.0 mA (with REXT1 = 2.94 K), over their operating range from +0.1V to -1.3V. Any voltage DAC used to drive these inputs directly needs to source at least 1.0 mA. Any current DAC used needs to factor in the constant 1.0 mA input current. The equation used to establish the VDELAY, VMID, and VFALL input currents is: I (VFALL, VDELAY, VMID) = 3.0V / REXT1. The fact that the VDELAY, VFALL, and VMID inputs have internal current sources allows a voltage DAC capable of generating only positive voltages and an external resistor network to be pulled down to the Edge142's negative input voltage compliance. These current sources are designed to be constant over temperature, so changes in system temperature will not translate into a delay voltage shift. Using a different REXT1 will program a different input current. However, the value of this current does not affect deskew range or performance. The ability to vary this current allows a more flexible interface to a variety of DAC programming techniques. VDELAY, VFALL, and VMID all require current flow. Do NOT leave any of these input pins floating. If an application does not require any falling edge delay, connect all VDELAY and VMID pins to ground.
Temperature coefficient = -10 mV/ C
Compensation Pins COMP1 and COMP2 are Op Amp compensation pins. For proper Edge142 functionality, these pins require a .1 F capacitor to ground.
Thermal Monitor The Edge142 includes an on-chip thermal monitor accessible through the pins TDP and TDN. These nodes connect to five diodes in series (see Figure 6) and may be used to accurately measure the junction temperature at any time.
TDP
Bias Current
TDN
Figure 6. Thermal Diode String An external bias current of 100 A is injected through the string, and the measured voltage corresponds to a specific junction temperature with the following equation: TJ(C) = {(V(TDP) - V(TDN)) / 5 - .7} / (-.00208).
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Application Information
Comparator Return Path The Edge142 is designed specifically to buffer, multiplex, and deskew multiple comparator paths from multiple test heads to the timing generators located back in the tester mainframe. The Edge142 provides a one IC solution between the pin electronics and the error strobing circuitry. Most importantly, the Edge142 performs all of the timing deskew functions, thus removing the burden of timing compensation from the error section. By performing the calibration with the Edge142, there may be some improvement in the edge to edge retrigger time inside the timing generator.
Chan N
Device Under Test
TIMING BOARD
Comp A
Edge142 4X2 Comp B
Comp A Timing Generator Comp B
Test Head 1
Device Under Test
Comp A Edge 142 Functions * Channel Multiplexing * Test Head Multiplexing * Comp A vs. Comp B Deskew * Chan N vs. Chan N + 1 Deskew * Test Head 1 vs. 2 Deskew * Rising vs. Falling Edge Deskew * Buffer Signals into Timing Board Performance Benefits * All Timing Lines - Point to Point Routing - Fully Differential * Single IC solution between P/E and TG
Comp B
Chan N + 1
Chan N
Device Under Test
Comp A
Comp B
Test Head 2
Device Under Test Comp A Comp A Edge142 4X2 Timing Generator Comp B
Comp B
Chan N + 1
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Application Information (continued)
Driver Fan Out The Edge142 is also designed to support the fanning out and deskewing of driver data, driver enable, and load enable signals to multiple test heads. By controlling PIN Descriptions the multiplexer and output enable signals, the signals may be routed to either test head. By using the Edge142 for timing calibration, the timing generator can generate "pure" timing signals, regardless of the timing errors associated with driving one test head vs. another. Removing the need for the timing generator to perform the deskew function, the restriction on consecutive edges may be improved.
TEST HEAD 1
Channel N
Device Under Test Edge142 Data Timing Generator Dvr Enable Mux Out 1 Out 1 Out 2 Mux Out 0
TEST HEAD 2 Edge 142 Functions * Test Head to Test Head Deskew - TG restrictions on edge regeneration improved * Driver Data vs. Enable Deskew * Rising vs. Falling Edge Deskew * Test Head Multiplexing * Cable Driver Performance Benefits * Point to Point Routing on all transmission lines
Channel N
Device Under Test
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Application Information (continued)
Temperature Coefficient The propagation delay temperature coefficient is shown in the above two charts. The same information is displayed on two different scales to enhance readability. The 142 functions over the entire VDELAY voltage range, but the timing error due to changes in the ambient temperature becomes large for VDELAY < -1.1V. If extreme accuracy is required, the recommended voltage range is: +0.1V >= VDELAY >= -1.1V. If greater range is needed and thermal drift can be tolerated, or the ambient temperature is very tightly controlled, the entire voltage range may be used.
Edge 142 Temperature Coefficient vs. VDELAY vs. Ambient
Temp Co [ps / C]
60 50 40 30 20 10 0 -0.1 -0.4 -0.8 VDELAY [V] -1.1 -1.3 Tpd- 50-60C Tpd- 40-50C Tpd+ 50-60C Tpd- 30-40C Tpd+ 40-50C Tpd+ 30-40C
Edge 142 Temperature Coefficient vs. VDELAY vs. Ambient
Temp Co [ps / C]
6 5 4 3 2 1 0 -0.1 -0.4 -0.8 VDELAY [V] -1.1 -1.3
Tpd+ 30-40C Tpd- 30-40C Tpd+ 40-50C Tpd- 40-50C Tpd+ 50-60C Tpd- 50-60C
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Application Information (continued)
Prop Delay vs. Frequency
EL11 Clock Spreader Tpd vs. Frequency
Error
The 142 shows very little change in propagation delay vs. frequency. The following three charts show the variation in the prop delay of a rising edge and a falling edge as the frequency is varied over a wide range. The first chart shows the Motorola 10EL11 clock spreader timing error for both the rising and falling edge with the input frequency varied from .5 MHz to 300 MHz. This information is used as a reference to compare the 142 against. The second and third charts show the 142 under identical conditions. The data is broken out into one chart for the rising edge and a separate chart for the falling edge. In addition, the timing error is listed over the entire delay range of the 142.
30 20
[ps]
10 0 -10 -20
0.5 10 20 50 75 100 125 150 200 250 300
Tpd+ Error Tpd- Error
Frequency [MHz]
Edge142 TPD+ Error vs. Frequency
VEE=-5.2V 30 VD=+0.1V 20 VD=-0.1V VD=-0.3V VD=-0.5V 0 VD=-0.7V VD=-0.9V VD=-1.1V -20 0.5 10 20 50 75 100 125 150 200 250 300 Frequency [MHz] VD=-1.3V VFALL & VMID=-0.6V
[ps] Error
10
-10
Edge142 TPD- Error vs. Frequency
VEE=-5.2V 30 VD=+0.1V 20 VD=-0.1V VD=-0.3V VD=-0.5V 0 VD=-0.7V VD=-0.9V VD=-1.1V -20 0.5 10 20 50 75 100 125 150 200 250 300 Frequency [MHz] VD=-1.3V VFALL & VMID=-0.6V
[ps] Error
10
-10
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Application Information (continued)
Prop Delay vs. Duty Cycle
EL11 Clock Spreader Tpd vs. 1%-99% Duty Cycle
The 142 shows very little change in propagation delay vs. input duty cycle. The following three charts show the variation in the prop delay of a rising edge and a falling edge as the duty cycle is varied from 1% to 99%. Since the input signal period is 100 ns, a 1% duty cycle corresponds to a 1 ns positive input pulse. A 99% duty cycle corresponds to a 1 ns negative input pulse. The first chart shows the Motorola 10EL11 clock spreader timing error for both the rising and falling edge. This information is used as a reference to compare the 142 against. The second and third charts show the 142 under identical conditions. The data is broken out into one chart for the rising edge and a separate chart for the falling edge. In addition, the timing error is listed over the entire delay range of the 142.
100 80 60
[ps]
40 20 0 -20 -40 -60 -80 -100
0 10 20 30 40 50 60 70 80 90 100 Tpd- Error Tpd+ Error
Error
Duty Cycle [%] (Period=100 ns)
Edge 142 Tpd+ vs. 1%-99% Duty Cycle
REXT2=2.94K 100 80 60
[ps]
Tpd+ Error, +0.1V Tpd+ Error, -0.1V Tpd+ Error, -0.3V Tpd+ Error, -0.7V Tpd+ Error, -0.9V Tpd+ Error, -1.1V Tpd+ Error, -1.3V 0 10 20 30 40 50 60 70 80 9 0 100 Duty Cycle [%] (Period=100 ns)
40 20 0 -20 -40 -60 -80 -100
Error
Edge 142 Tpd- vs. 1%-99% Duty Cycle
REXT2=2.94K 100 80 60
[ps]
Tpd- Error, +0.1V Tpd- Error, -0.1V Tpd- Error, -0.3V Tpd- Error, -0.7V Tpd- Error, -0.9V Tpd- Error, -1.1V Tpd- Error, -1.3V 0 10 20 30 40 50 60 70 80 9 0 100 Duty Cycle [%] (Period=100 ns)
40 20 0 -20 -40 -60 -80 -100
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Error
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Package Information
4 D D2 D 3
4X
0.25
C
A-B
D
3
A E E2 B 3 4
e
SEE DETAIL "A"
TOP VIEW
5 D1 Z D
7
C
O
E1
5
7
O
2 Z 4X E 0.20
5 C
7 A-B D
BOTTOM VIEW
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Package Information (continued)
0.40 MIN. 0 MIN.
e
A2 - 0.10 S 0.13 R. MIN. 0.13 / 0.30 R.
C 0.25
GAGE PLANE
-A, B, D-
3
A1 L 1.60 REF. C 0-7
DETAIL "A"
DETAIL "B"
12 - 16
A
SEE DETAIL "B" b
8
ccc
M C A-B S D S WITH LEAD FINISH
1.41 REF.
H
2 0.076
12 0.13 / 0.23
0.13 / 0.17
C 12 - 16
SECTION C-C
b 1
BASE METAL
Notes: 1. All dimensions and tolerances conform to ANSI Y14.5-1982. 2. Datum plane -H- located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and -D- to be determined where centerline between leads exits plastic body at datum plane -H-. 4. To be determined at seating plane -C-. 5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 mm per side. Dimensions D1 and E1 do include mold mismatch and are determined at datum plan -H-. 6. "N" is the total # of terminals. 7. Package top dimensions are smaller than bottom dimensions by 0.20 mm, and top of package will not overhang bottom of package. 8. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 9. All dimensions are in millimeters. 10. Maximum allowable die thickness to be assembled in this package family is 0.635 millimeters. 11. This drawing conforms to JEDEC registered outline MS-108. 12. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 2000 Semtech Corp.
JEDEC VARIATION All Dimensions in Millimeters AC Min. Nom. Max. Note Comments A 2.15 2.35 Soldered PkgHeight above PCB A1 0.10 0.15 0.25 PCB Clearance A2 1.95 2.00 2.10 Package Body Thickness D 4 13.20 BSC. D1 5 Package Body Length 10.00 BSC. D2 7.80 REF. ZD 1.10 REF. E 4 13.20 BSC. E1 5 Package Body Width 10.00 BSC. E3 7.80 REF. ZE 1.10 REF. L 0.73 0.88 1.03 N 52 6 # Pins e 0.65 Lead Pitch b 0.22 0.38 b1 0.22 0.30 0.33 aaa 0.12
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Recommended Operating Conditions
Parameter Device Ground Negative Power Supply Ambient Operating Temperature
Symbol GND VEE TA
Min 0 -4.2 0
Typ 0 -5.2
Max 0 -5.5 +70
Units V V
o
C
Absolute Maximum Ratings
Parameter VEE (relative to GND) Voltage on any Digital Pin Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) TA TS TJ TSOL Symbol Min -7.0 VEE -50 -55 -65 +70 +150 +150 260 Typ Max 0 GND Units V V mA
o o o o
C C C C
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS DC Characteristics
Parameter Inputs Differential Digital Input High Voltage IN, IN* Differential Digital Input Low Voltage IN, IN* Digital Input High Voltage S00, S01, S10, S11, MODE, EN*, MUX SEL, MUX EN Digital Input Low Voltage S00, S01, S10, S11, MODE, EN*, MUX SEL, MUX EN Input Common Mode Range Input High Current (Vin = VIHmax) Input Low Current (Vin = VILmin) VDELAY, VFALL, & VMID Input Currents Outputs OUT0 / OUT0*, OUT1 / OUT1* MUX OUT0 / MUX OUT0*, MUX OUT1 / MUX OUT1* Digital Output High Voltage Digital Output Low Voltage Output Common Mode Range OUT - OUT* OUT* - OUT OUT + OUT* 2 700 700 -1.1 800 800 -1.35 -1.5 mV mV V IN - IN* IN* - IN VIH 300 300 -1070 0 mV mV mV Symbol Min Typ Max Units
VIL
VEE
-1450
mV
IN, IN* IIH IIL Iin
-2.0 -100 -100 .84 120 90 .990
-0.5 250 150 1.08
V A A mA
VEE Supply Current VEE = -4.5V VEE = -5.0V VEE = -5.5V IEE IEE IEE -255 -260 -265 -200 -205 -210 -155 -160 -165 mA mA mA
Test conditions (unless otherwise specified): "Recommended Operating Conditions" with REXT1 = 2.94 K, and REXT2 = 2.94 K. All parameters specified at 0C are guaranteed by characterization and are not production tested. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device mounted either in the test socket or on the printed circuit board.
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS AC Characteristics
Parameter Propagation Delays Minimum Delay (Pulse Width >= 1.0 ns) VDELAY = +0.1V, VFALL = +0.1V Delay Range vs. Pulse Width Input Pulse Width >= 1.0 ns (+0.1V < VDELAY < -1.2V) VFALL Range of Adjustment Input Pulse Width >= 1.0 ns (+0.1V < VFALL < -1.2V) Propagation Delay Tempco (Note 1) -1.1V <= VDELAY, VFALL <= +0.1V Output Rise/Fall Times (20% to 80%) (Note 1) Tr, Tf 300 Symbol Min Typ Max Units
TPDmin
1.75
2.05
2.45
ns
Tspan
1.1
1.4
ns
Tfall
170
300
ps
<2 420 500
ps / oC ps
Test conditions (unless otherwise specified): "Recommended Operating Conditions" with TA = 25 C with 400 LFPM of airflow, and all outputs terminated with 50 to -2.0 V. Timing reference points at the differential crossing points for input and output signals, REXT1 = 2.94 K, and REXT2 = 2.94 K. All input signals are fully differential. Values are based on nominal temperature and a supply voltage of -5.2 V. Note 1: Based upon characterization data. Not production tested. For more complete data, refer to the application information section of the data sheet. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device mounted either in the test socket or on the printed circuit board.
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Edge142
EDGE HIGH-PERFORMANCE PRODUCTS Ordering Information
Model Number
Package 52 Pin 10mm x 10mm MQFP with Internal Heat Spreader Die Form
E142AHF
D142
EVM142AHF
Edge142 Evaluation Module
Contact Information
Semtech Corporation Edge High-Performance Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1801 FAX (858)695-2633
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